TY - GEN
T1 - 2D Physical Modelling of Double δ-Doped pHEMT with Tensile InAlAs Barrier and Compressive InGaAs Channel
AU - Ikhwan, Nur Iwana Mohd
AU - Mohamed, Mohamed Fauzi Packeer
AU - Khan, Muhammad Firdaus Akbar Jalaludin
AU - Ghazali, Nor Azlin
AU - Manaf, Asrulnizam Abd
AU - Baharin, Mohd Syamsul Nasyriq Samsol
AU - Hairi, Mohd Hendra
AU - Rahim, Alhan Farhanah Abd
N1 - Publisher Copyright:
© 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
PY - 2022
Y1 - 2022
N2 - This study focuses on the optimization of fabricated 1 µm gate length depletion-mode double δ-doped In0.3Al0.7As/ In0.7Ga0.3As/InP depletion-mode pHEMT using SILVACO ATLAS TCAD simulator. Physical modelling of the pHEMT devices is required to further understand the effect of the parameters and structures on the device performance, which incorporated a highly tensile In0.3Al0.7As barrier and compressive In0.7Ga0.3As channel. The work starts with developing a base model from the fabricated device DC characteristic such as I-V curves by inverse modelling and matching simulated results with measured results. Finally, to study the effects of channel layer thicknesses and gate length variations, the models are simulated, and the corresponding I-V curves are compared to the base model. Hence, by increasing the channel layer thickness by 15% from its original thickness and reducing the 1 um gate length by 60%, the channel layer and gate length were successfully simulated and agreed well with the measured results.
AB - This study focuses on the optimization of fabricated 1 µm gate length depletion-mode double δ-doped In0.3Al0.7As/ In0.7Ga0.3As/InP depletion-mode pHEMT using SILVACO ATLAS TCAD simulator. Physical modelling of the pHEMT devices is required to further understand the effect of the parameters and structures on the device performance, which incorporated a highly tensile In0.3Al0.7As barrier and compressive In0.7Ga0.3As channel. The work starts with developing a base model from the fabricated device DC characteristic such as I-V curves by inverse modelling and matching simulated results with measured results. Finally, to study the effects of channel layer thicknesses and gate length variations, the models are simulated, and the corresponding I-V curves are compared to the base model. Hence, by increasing the channel layer thickness by 15% from its original thickness and reducing the 1 um gate length by 60%, the channel layer and gate length were successfully simulated and agreed well with the measured results.
KW - InGaAs/InAlAs/InP
KW - Semiconductor device
KW - Silvaco
KW - pHEMT
UR - http://www.scopus.com/inward/record.url?scp=85125255123&partnerID=8YFLogxK
U2 - 10.1007/978-981-16-8129-5_135
DO - 10.1007/978-981-16-8129-5_135
M3 - Conference contribution
AN - SCOPUS:85125255123
SN - 9789811681288
T3 - Lecture Notes in Electrical Engineering
SP - 884
EP - 889
BT - Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications - Enhancing Research and Innovation through the Fourth Industrial Revolution
A2 - Mahyuddin, Nor Muzlifah
A2 - Mat Noor, Nor Rizuan
A2 - Mat Sakim, Harsa Amylia
PB - Springer Science and Business Media Deutschland GmbH
T2 - 11th International Conference on Robotics, Vision, Signal Processing and Power Applications, RoViSP 2021
Y2 - 5 April 2021 through 6 April 2021
ER -