TY - GEN
T1 - 3D video coding development based on FPGA platform Xilinx zynq-7000
AU - Bukit, Alexander Victor
AU - Wirawan,
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/11/28
Y1 - 2017/11/28
N2 - Digital video compression techniques have an important role that makes transmission and storage of multimedia content in bandwidth and storage space limited environment efficient. This paper describes 3D video coding using FPGA encoder architecture for newer and more reliable multimedia technologies to drive the industry to improve services in the field of entertainment marketing, to encourage the popularization of 3D video content, supporting devices 3D capabilities, and 3D applications. As a phenomenon that occurs at this time, smartphones, tablets, and other mobile devices has surpassed the value of PC sales. Along with the growing popularity of 3D video and be applied to the mobile device, resulting in the need for storage, data transmission, and display requires an efficient coding. The design is described in VHDL and synthesized to Zynq 7000 AP SoC FPGA. The throughput of the FPGA architecture reaches a processing at 666 MHz, RAM frequency 533 MHz permitting its use in H.265/HEVC standard directed to HDTV. To improve reliability in the process of encoder, one of which can be done by implementing a code HEVC to Zynq 7000 AP SoC.
AB - Digital video compression techniques have an important role that makes transmission and storage of multimedia content in bandwidth and storage space limited environment efficient. This paper describes 3D video coding using FPGA encoder architecture for newer and more reliable multimedia technologies to drive the industry to improve services in the field of entertainment marketing, to encourage the popularization of 3D video content, supporting devices 3D capabilities, and 3D applications. As a phenomenon that occurs at this time, smartphones, tablets, and other mobile devices has surpassed the value of PC sales. Along with the growing popularity of 3D video and be applied to the mobile device, resulting in the need for storage, data transmission, and display requires an efficient coding. The design is described in VHDL and synthesized to Zynq 7000 AP SoC FPGA. The throughput of the FPGA architecture reaches a processing at 666 MHz, RAM frequency 533 MHz permitting its use in H.265/HEVC standard directed to HDTV. To improve reliability in the process of encoder, one of which can be done by implementing a code HEVC to Zynq 7000 AP SoC.
KW - H.265
KW - HEVC
KW - Vivado
KW - Xilinx
KW - Zynq
UR - http://www.scopus.com/inward/record.url?scp=85043514461&partnerID=8YFLogxK
U2 - 10.1109/ISITIA.2017.8124050
DO - 10.1109/ISITIA.2017.8124050
M3 - Conference contribution
AN - SCOPUS:85043514461
T3 - 2017 International Seminar on Intelligent Technology and Its Application: Strengthening the Link Between University Research and Industry to Support ASEAN Energy Sector, ISITIA 2017 - Proceeding
SP - 29
EP - 34
BT - 2017 International Seminar on Intelligent Technology and Its Application
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th International Seminar on Intelligent Technology and Its Application, ISITIA 2017
Y2 - 28 August 2017 through 29 August 2017
ER -