A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS

Andrew Nicholson, Julian Jenkins, Astria Nur Irfansyah, Nonie Politi, Andre Van Schaik, Tara Julia Hamilton, Torsten Lehmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Citations (Scopus)

Abstract

We present a standard pipelined ADC design using Nauta structure differential op-amps as an alternative to traditional analog op-amps. The six stage pipelined ADC is capable of running at 100MS/s and achieves 8 bit resolution under simulations. The research is focused on the path to scaling to deep sub-micron CMOS and finding alternatives to the reduced gain and low output voltage swing of traditional analog op-amp designs. The Nauta structure op-amp allows us to produce one of the smallest reported areas for a 180nm pipelined ADC occupying only 0.3mm2 for a 10 bit 100MS/s pipelined ADC.

Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages1833-1836
Number of pages4
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 19 May 201323 May 2013

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Country/TerritoryChina
CityBeijing
Period19/05/1323/05/13

Keywords

  • 180nm CMOS
  • Analog to Digital Conversion
  • Nauta structure
  • Pipelined ADC

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