A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching

Astria Nur Irfansyah*, Torsten Lehmann, Julian Jenkins, Tianle Tong, Tara Julia Hamilton

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


This paper presents a study and implementation of a shunt–shunt resistive voltage divider digital-to-analog converter (DAC) for use as a multibit DAC in a multi-stage noise shaping sigma-delta modulator DAC design with dynamic element matching. This resistive DAC structure is employed to address the problem of code-dependent finite output impedance and thus aims to improve systematic linearity, while still being suitable for scaled CMOS processes. Chip measurement results from an implementation in CMOS 180 nm technology are presented. At low sampling clock frequencies, an SFDR of 71.81 dB is achieved, while at a higher sampling clock frequency of 600 MHz the SFDR is measured to be 59.73 dB, all for an OSR of 32. Our results show that low systematic nonlinearity can be achieved with this resistive DAC at low sampling frequencies, and we discuss potential enhancements to our prototype to obtain better SFDR at higher sampling rate.

Original languageEnglish
Pages (from-to)109-123
Number of pages15
JournalAnalog Integrated Circuits and Signal Processing
Issue number1
Publication statusPublished - 15 Jan 2019


  • DAC
  • Dynamic element matching
  • MASH
  • Sigma-delta


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