Numerical Control Oscillator (NCO) is a main component to generate a signal. The uses of NCO is widely increased because of its simplicity of use and able to obtain high precision signal. One of many methode used by NCO is CORDIC algorithm. Coordinate Rotation Digital Computer (CORDIC) is one of many popular method used in trigonometric calculation and digital signal processing. It is said that this algorithm has a high efficiency for hardware implementation. CORDIC is often used as a core of DDS (Direct Digital Synthesis) to generate a signal. In this research, a sinusoidal wave is generated using 16 stages pipelined CORDIC algorithm system with look-up table. The system is designed using Intel ALTERA FPGA Cyclone II and its RTL model is simulated using ModelSim. The results show that the system is able to generate the signal with approximately 0.42% of error, and the proposed pipelined architecture is able to increase the systems maximum restricted clock speed from 8.2 MHz to 89.17 MHz.