TY - GEN
T1 - Design of Sinusoidal Signal Generator Using Pipelined CORDIC Architecture Based on Altera Cyclone II FPGA
AU - Raditya, Murry
AU - Darwito, Purwadi Agus
AU - Cikadiarta, Arviandi
AU - Sa'Diyah, Halimatus
AU - Wimansyah, Aditya
AU - Rajagukguk, Effran
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - Numerical Control Oscillator (NCO) is a main component to generate a signal. The uses of NCO is widely increased because of its simplicity of use and able to obtain high precision signal. One of many methode used by NCO is CORDIC algorithm. Coordinate Rotation Digital Computer (CORDIC) is one of many popular method used in trigonometric calculation and digital signal processing. It is said that this algorithm has a high efficiency for hardware implementation. CORDIC is often used as a core of DDS (Direct Digital Synthesis) to generate a signal. In this research, a sinusoidal wave is generated using 16 stages pipelined CORDIC algorithm system with look-up table. The system is designed using Intel ALTERA FPGA Cyclone II and its RTL model is simulated using ModelSim. The results show that the system is able to generate the signal with approximately 0.42% of error, and the proposed pipelined architecture is able to increase the systems maximum restricted clock speed from 8.2 MHz to 89.17 MHz.
AB - Numerical Control Oscillator (NCO) is a main component to generate a signal. The uses of NCO is widely increased because of its simplicity of use and able to obtain high precision signal. One of many methode used by NCO is CORDIC algorithm. Coordinate Rotation Digital Computer (CORDIC) is one of many popular method used in trigonometric calculation and digital signal processing. It is said that this algorithm has a high efficiency for hardware implementation. CORDIC is often used as a core of DDS (Direct Digital Synthesis) to generate a signal. In this research, a sinusoidal wave is generated using 16 stages pipelined CORDIC algorithm system with look-up table. The system is designed using Intel ALTERA FPGA Cyclone II and its RTL model is simulated using ModelSim. The results show that the system is able to generate the signal with approximately 0.42% of error, and the proposed pipelined architecture is able to increase the systems maximum restricted clock speed from 8.2 MHz to 89.17 MHz.
KW - CORDIC algorithm
KW - FPGA
KW - Intel Altera
KW - Pipelined architecture
UR - http://www.scopus.com/inward/record.url?scp=85095822209&partnerID=8YFLogxK
U2 - 10.1109/ICAMIMIA47173.2019.9223410
DO - 10.1109/ICAMIMIA47173.2019.9223410
M3 - Conference contribution
AN - SCOPUS:85095822209
T3 - 2019 International Conference on Advanced Mechatronics, Intelligent Manufacture and Industrial Automation, ICAMIMIA 2019 - Proceeding
SP - 105
EP - 108
BT - 2019 International Conference on Advanced Mechatronics, Intelligent Manufacture and Industrial Automation, ICAMIMIA 2019 - Proceeding
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 International Conference on Advanced Mechatronics, Intelligent Manufacture and Industrial Automation, ICAMIMIA 2019
Y2 - 9 October 2019 through 10 October 2019
ER -