Energy delay optimization methodology for current-mode signaling for on-chip interconnects

Astria Nur Irfansyah, Torsten Lehmann, Saeid Nooshabadi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend on each other. The methodology will be validated using the SPICE simulations. It will be shown that when dealing with the receiver termination sizing, the optimal size is determined by the voltage swing required by the noise margin.

Original languageEnglish
Title of host publicationProceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages147-150
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
EventIEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Minatec Grenoble, France
Duration: 2 Jun 20084 Jun 2008

Publication series

NameProceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Conference

ConferenceIEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008
Country/TerritoryFrance
CityMinatec Grenoble
Period2/06/084/06/08

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