TY - GEN
T1 - Five-Stage Pipelined 32-Bit RISC-V Base Integer Instruction Set Architecture Soft Microprocessor Core in VHDL
AU - Phangestu, Aaron Elson
AU - Mujiono, Ir Totok
AU - Kom, M. I.
AU - Ahmad Zaini, St
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Proprietary technologies with complicated licensing currently dominate the microprocessor industry. As a result, we must seek out a freely available, open-source alternative. In this paper, we discussed the implementation of a five-stage pipelined soft processor core. The core uses the RISC-V RV32I Base Integer Instruction Set Architecture. RISC-V is an open standard ISA that is freely available to use and modify. To implement our processor core, we followed the FPGA design methodology. First, we implemented the design specification with the VHDL Hardware Description Language. Then, siwe mulated the design in the ModelSim simulation environment. Following the verification, we analyzed the resource usage, critical path, and maximum frequency of the processor, then uploaded the processor core to an actual Cyclone IV EP4CE6E22C FPGA. Our CPU core successfully executed all the RV32I instructions, except FENCE, ECALL, and CSR instructions. The proposed processor core runs on 2115 LUTs, 558 flip-flops, and 67,608 memory bits, with a maximum frequency of 62.95 MHz.
AB - Proprietary technologies with complicated licensing currently dominate the microprocessor industry. As a result, we must seek out a freely available, open-source alternative. In this paper, we discussed the implementation of a five-stage pipelined soft processor core. The core uses the RISC-V RV32I Base Integer Instruction Set Architecture. RISC-V is an open standard ISA that is freely available to use and modify. To implement our processor core, we followed the FPGA design methodology. First, we implemented the design specification with the VHDL Hardware Description Language. Then, siwe mulated the design in the ModelSim simulation environment. Following the verification, we analyzed the resource usage, critical path, and maximum frequency of the processor, then uploaded the processor core to an actual Cyclone IV EP4CE6E22C FPGA. Our CPU core successfully executed all the RV32I instructions, except FENCE, ECALL, and CSR instructions. The proposed processor core runs on 2115 LUTs, 558 flip-flops, and 67,608 memory bits, with a maximum frequency of 62.95 MHz.
KW - FPGA
KW - RISC-V
KW - RV32I
KW - VHDL
KW - five-stage pipeline
KW - soft processor core
UR - http://www.scopus.com/inward/record.url?scp=85137936655&partnerID=8YFLogxK
U2 - 10.1109/ISITIA56226.2022.9855292
DO - 10.1109/ISITIA56226.2022.9855292
M3 - Conference contribution
AN - SCOPUS:85137936655
T3 - 2022 International Seminar on Intelligent Technology and Its Applications: Advanced Innovations of Electrical Systems for Humanity, ISITIA 2022 - Proceeding
SP - 304
EP - 309
BT - 2022 International Seminar on Intelligent Technology and Its Applications
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd International Seminar on Intelligent Technology and Its Applications, ISITIA 2022
Y2 - 20 July 2022 through 21 July 2022
ER -