TY - GEN
T1 - Sine wave synthesis with harmonic-cancellation and single-bit Sigma-Delta modulation
AU - Irfansyah, Astria Nur
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/1
Y1 - 2017/7/1
N2 - Sinusoidal waveform generation as part of an on-chip built-in self-test (BIST) system typically requires sufficient linearity without excessive hardware overhead. This paper investigates the use of staircase waveform from summation of phase-shifted square waves for sine wave synthesis with its harmonic cancellation properties combined with single-bit sigmadelta modulation for a reduced complexity yet highly digital implementation suitable for such BIST scenario. A prototype system implemented in an Intel Altera Cyclone V FPGA is presented to verify the proposed approach, with experimental results showing the output spectrum of the generated sine wave signal with 44.8-dB spurious-free dynamic range (SFDR) with a system clock running at 50 MHz.
AB - Sinusoidal waveform generation as part of an on-chip built-in self-test (BIST) system typically requires sufficient linearity without excessive hardware overhead. This paper investigates the use of staircase waveform from summation of phase-shifted square waves for sine wave synthesis with its harmonic cancellation properties combined with single-bit sigmadelta modulation for a reduced complexity yet highly digital implementation suitable for such BIST scenario. A prototype system implemented in an Intel Altera Cyclone V FPGA is presented to verify the proposed approach, with experimental results showing the output spectrum of the generated sine wave signal with 44.8-dB spurious-free dynamic range (SFDR) with a system clock running at 50 MHz.
UR - http://www.scopus.com/inward/record.url?scp=85047551268&partnerID=8YFLogxK
U2 - 10.1109/ISESD.2017.8253322
DO - 10.1109/ISESD.2017.8253322
M3 - Conference contribution
AN - SCOPUS:85047551268
T3 - 2017 International Symposium on Electronics and Smart Devices, ISESD 2017
SP - 150
EP - 153
BT - 2017 International Symposium on Electronics and Smart Devices, ISESD 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd International Symposium on Electronics and Smart Devices, ISESD 2017
Y2 - 17 October 2017 through 19 October 2017
ER -