Abstract

This paper deals with the implementation of a stochastic flash ADC with the presence of comparator metastability, in a field-programmable gate array. Stochastic flash ADC exploits comparator threshold variation and can be implemented with simple and highly digital structures. We show that such designs is also prone to comparator metastability, therefore we propose an averaging scheme as a simple means to handle the situation. Experimental results from a prototype system based on an FPGA is given which shows the effectiveness of the averaging technique, resulting in a maximum measured SNDR of 22.24 dB with a sampling rate of 98 kHz.

Original languageEnglish
Title of host publicationProceedings of the 2nd International Conference on Automation, Cognitive Science, Optics, Micro Electro-Mechanical System, and Information Technology, ICACOMIT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages75-79
Number of pages5
ISBN (Electronic)9781538605103
DOIs
Publication statusPublished - 1 Jul 2017
Event2nd International Conference on Automation, Cognitive Science, Optics, Micro Electro-Mechanical System, and Information Technology, ICACOMIT 2017 - Jakarta, Indonesia
Duration: 23 Oct 2017 → …

Publication series

NameProceedings of the 2nd International Conference on Automation, Cognitive Science, Optics, Micro Electro-Mechanical System, and Information Technology, ICACOMIT 2017
Volume2018-January

Conference

Conference2nd International Conference on Automation, Cognitive Science, Optics, Micro Electro-Mechanical System, and Information Technology, ICACOMIT 2017
Country/TerritoryIndonesia
CityJakarta
Period23/10/17 → …

Keywords

  • Analog-digital conversion
  • field programmable gate arrays
  • mixed analog digital integrated circuits
  • stochasticpro- cesses

Fingerprint

Dive into the research topics of 'Stochastic flash ADC considering comparator metastability implemented in FPGA'. Together they form a unique fingerprint.

Cite this